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INTEGRATED CIRCUITS
PCA9558 8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
Product data Supersedes data of 2000 Dec 04 2002 May 24
Philips Semiconductors
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
set of inputs provided by the I2C/SMBus interface and stored in the EEPROM. Examples of this type of selection include processor voltage configuration or processor vendor identification (VID). The multiplexed/latched EEPROM can also be used to replace DIP switches or jumpers, since the settings can be easily changed via I2C/SMBus without having to power down the equipment to open the cabinet. The non-volatile memory retains the most current setting selected before the power is turned off. 8-bit I/O expander -- used to control, monitor or collect remote information or power LEDs. Monitored or collected information can be read through the I2C/SMBus or can be stored in the internal EEPROM. 2K serial EEPROM -- used to store information such as card identification or revision/maintenance history on every motherboard/linecard and can be read or written via I2C/SMBus when required. The PCA9558 has 1 address pin allowing up to 2 devices to be placed on the same I2C bus or SMBus.
FEATURES
* 5-bit 2-to-1 multiplexer, 1-bit latch * 6-bit MUX_OUTx and NON_MUXED_OUT EEPROM *
programmable and readable via I2C-bus 5 V tolerant open drain MUX_OUTx and NON_MUXED_OUT outputs Active-LOW override input forces all MUX_OUTx outputs to logic 0
* * I2C readable MUX_INx inputs * 5 V tolerant open drain I/Ox pins, power-up default as outputs * 1 address pin, allowing up to 2 devices on the I2C-bus * Active-LOW reset input with internal pull-up for the 8 I/O pins * 2048-bit EEPROM programmable and readable via the I2C or I/Os * Operating power supply voltage range of 3.0 V - 3.6 V * SMBus compliance with fixed 3.3 V levels * 2.5 V - 5 V tolerant inputs
PIN CONFIGURATION
SCL 1 SDA 2 28 VDD 27 WP 26 MUX_OUT_LOW 25 NON_MUXED_OUT 24 MUX_OUTA 23 MUX_OUTB 22 MUX_OUTC 21 MUX_OUTD 20 MUX_OUTE 19 MUX_SELECT 18 I/O7 17 I/O6 16 I/O5 15 I/O4
I/O_OUT_LOW 3 A0 MUX_INA MUX_INB 4 5 6
* ESD protection exceeds 2000 V HBM per JESD22-A114,
exceeds 100 mA
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
* Latch-up testing is done to JESDEC Standard JESD78 which
DESCRIPTION
The PCA9558 is a highly integrated, multi-function device that is composed of a 5-bit multiplexed/1-bit latched 6-bit I2C/SMBus EEPROM, an 8-bit I/O expander and a 2K serial EEPROM with write protect. The PCA9558 integrates these commonly used components into a single chip to reduce component count and board space requirements and is useful in computer, server and telecom/networking applications. Multiplexed/latched EEPROM -- used to select digital information between a set of 5-bits of default hardware inputs and an alternative
MUX_INC 7 MUX_IND 8 MUX_INE 9
GND 10 I/O0 11 I/O1 12 I/O2 13 I/O3 14
SW00614
ORDERING INFORMATION
PACKAGES 28-Pin Plastic TSSOP TEMPERATURE RANGE 0 to +70 C ORDER CODE PCA9558PW DRAWING NUMBER SOT361-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2002 May 24
2
853-2235 28310
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
PIN DESCRIPTION
PIN NUMBER 1 2 3 4 5-9 10 11-18 19 20-24 25 26 27 28 SYMBOL SCL SDA I/O_OUT_LOW A0 MUX_IN A-E GND I/O[0-7] MUX_SELECT MUX_OUT E-A NON_MUXED_OUT MUX_OUT_LOW WP VDD Serial I2C bus clock Serial bi-directional I2C bus data Active-LOW control forces all GPIO to logic 0 outputs A0 Address External inputs to multiplexer Ground General purpose Input/Output 0 through 7 (open drain outputs) Active-LOW Select of MUX_IN inputs or EEPROM contents for MUX_OUT outputs Open drain multiplexed outputs Open drain outputs from non-volatile memory Active-LOW control forces all MUX outputs to logic 0 Active-HIGH EEPROM write protect Power supply : +3.0 to +3.6 V FUNCTION
2002 May 24
3
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
BLOCK DIAGRAM
PCA9558
MUX SELECT
MUX_OUT_LOW 6-BIT EEPROM NON_MUXED_OUT LATCH 5
MUX_IN
1 MUX_OUTA A0 MUX_OUTB 5-BIT 2 TO 1 MULTIPLEXER I2C INTERFACE LOGIC INPUT FILTER 5 0 MUX_OUTC MUX_OUTD MUX_OUTE
SCL SDA
VDD
POWER-ON RESET
I2C CONTROL LOGIC
GND GPIO 8 256 BYTE EEPROM I/O0-7
WRITE PROTECT
I/O_OUT_LOW
SW00633
2002 May 24
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
I2C INTERFACE
PCA9558
Communicating with this device is initiated by sending a valid address on the I2C bus. The address format (see FIgure 1) has 6 fixed bits and one user-programmable bits followed by a 1-bit read/write value which determines the direction of the data transfer.
MSB
LSB
1
0
0
1
1
1
A0
R/W#
SW00615
Figure 1.
I2 C
Address Byte
Following the address and acknowledge bit are 8 data bits which, depending on the read/write bit in the address, will read data from or write data to the EEPROM. Data will be written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be read from the register if the bit is logic 1. The four high-order bits are latched outputs, while the four low order bits are multiplexed outputs (Figure 3). NOTE: 1. To ensure data integrity, the EEPROM must be internally write protected when VCC to the I2C bus is powered down or VCC to the component is dropped below normal operating levels.
MSB
LSB
MSB LSB 0000 0001 0000 0011 0000 0100 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1101 0000 1110 0000 1111 0001 0000 0001 0001 0001 0010 0001 0011 to 1111 1111
Write to 256EE via I2C Read from 256EE via I2C Write to 6bitEE via I2C Read from 6bitEE via I2C Read IP (Input Port) Register via I2C Read/Write OP (Output Port) Register via I2C Read/Write PI (Polarity Inversion) Register via I2C Read/Write IOC (Input/Output Configuration Register via I2C Read/Write MUXCNTRL (Mux Control) Register via I2C Read MUXIN values via I2C Reserved Reserved Read 256EE and Write OP Register Read 256EE and Write PI Register Read 256EE and Write IOC Register Read IP Register and Write to 256EE Reserved Reserved
SW00634
Figure 2. Command Byte
MSB
LSB
0
0
Non_muxed Data
Mux Data E
Mux Data D
Mux Data C
Mux Data B
Mux Data A
SW00456
Figure 3. I2C MUX_OUT Data Byte
MSB
LSB
0
0
0
MUX_IN E
MUX_IN D
MUX_IN C
MUX_IN B
MUX_IN A
SW00528
Figure 4.
I 2C
MUX_IN Data Byte
2002 May 24
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
The Multiplexer function controls the six open drain outputs, MUX_OUTx and NON_MUXED_OUT. This control is effected by the input pins MUX_SELECT (Pin 19), MUX_OUT_LOW (Pin 26), and/or an internal register programmed via the I2C-bus. Upon power-up the multiplex function is controlled by the MUX_SELECT and MUX_OUT_LOW pins. When the MUX_SELECT signal is a logic 0, the multiplexer will select the data from the 6-bit EEPROM to drive on the MUX_OUTx and NON_MUXED_OUT pins. When the MUX_SELECT signal is a logic 1, the multiplexer will select the MUX_INx pins to drive on the MUX_OUTx pins. The NON_MUXED_OUT output is latched from the 6-bit EEPROM on a rising edge of the MUX_SELECT signal. This latch is transparent while the MUX_SELECT signal is a logic 0. An internal control register, written via the I2C bus, can also control the multiplexer function. When this register is written, the MUX_SELECT function can change from the external pin to an internal register. In this register a bit will act in a similar fashion to the MUX_SELECT input, i.e., a logic 1 will cause the multiplexer to select data from the 6-bit EEPROM to drive on the MUX_OUTx and NON_MUXED_OUT pins. In this configuration, the NON_MUXED_OUT will latch data when the PCA9558 acknowledges the I2C-bus. The MUX_SELECT pin will have no effect on the MUX_OUTx or NON_MUXED_OUT while in this mode. When the MUX_OUT_LOW signal is a logic 0 and the multiplexer is configured so that the MUX_OUTx pins are being driven by the 6-bit EEPROM, the MUX_OUTx pins will be driven to a logic 0. This information is summarized in Table 1.
Table 1. Multiplexer function table
REG. B13 x x x x 0 1 0 1 B03 0 0 0 0 1 1 1 1 MUX_OUT_LOW 0 0 1 1 0 0 1 1 INPUT MUX_SELECT 1 0 1 0 x x x x MUX_OUTx MUX_INx inputs 0 MUX_INx inputs from EEPROM MUX_INx inputs 0 MUX_INx inputs from EEPROM OUTPUT NON_MUXED_OUT latched from EEPROM1 0 latched from EEPROM1 from EEPROM latched from EEPROM2 0 latched from EEPROM2 from EEPROM
NOTES: 1. NON_MUXED_OUT value will be the value present in the 6-bit EEPROM at the time of the rising edge of the MUX_SELECT input. 2. NON_MUXED_OUT value will be the value present int he 6-bit EEPROM at the time of the slave ACK when bit1 has changed from 0 to 1. 3. These are the 2LSBs of the MUXCNTRL (Mux Control) Register If the MUX_OUTx outputs are being driven by the 6-bit EEPROM and this EEPROM is programmed, the outputs will remain stable and change to the new values after the EEPROM program cycle completes. Examples of Read/Write for MUX control can be found in Figure 5.
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
S
1
0
0
1
1
1 A0 0
A
0
0
0
0
1
0
1
1
A
0
0
0
0
0
0 B1 B0 A
P
SLAVE ADDRESS R/W
COMMAND BYTE
DATA BYTE
SW00635
Figure 5. I2C write for MUXCNTRL register
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
NO ACKNOWLEDGE FROM MASTER
S
1
0
0
1
1
1 A0 0
A
0
0
0
0
1
0
1
1
A
S
1
0
0
1
1
1 A0 1
A
0
0
0
0
0
0 B1 B0 NA P
SLAVE ADDRESS R/W
COMMAND BYTE
SLAVE ADDRESS R/W
DATA FROM SLAVE
SW00636
Figure 6.
I 2C
read for MUXCNTRL register
2002 May 24
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
The GPIOs are controlled by a set of 4 internal registers: Input Port Register (IPR); Output Port Register (OPR); Polarity Inversion Register (PIR); and the Input/Output Configuration Register (IOCR). Each register is read/write via the I2C-bus or 256 byte EEPROM, with the exception of the IPR, which is read only, one at a time. The read/write takes place on the slave ACKNOWLEDGE. The control of which register is currently available to the I2C-bus is set by bits in the control register. See Tables 2 through 5 for details.
Table 2. Input Port Register (IPR)
Bit Default I7 0 I6 0 I5 0 I4 0 I3 0 I2 0 I1 0 I0 0
Table 5. I/O Configuration Register (IOCR)
Bit Default C7 0 C6 0 C5 0 C4 0 C3 0 C2 0 C1 0 C0 0
This register is an input-only port. It reflects the logic value present on the GPIO pins regardless of whether they are configured as inputs or outputs (IOCR). Writes to this register have no effect.
This register configures the direction of the GPIO pins. If a bit is set to a logic 1, the corresponding port pin is enabled as an input with a high impedance output driver. If a bit is set to a logic 0, the corresponding port pin is enabled as an output. Examples of Read/Write to these registers can be found in Figures 7, 8, 13, and 14. The I/O_OUT_LOW input, when held LOW longer than the time tW, will reset the GPIO registers to their default (power-up) values. A read of the present value of the inputs MUX_INx can be done via the I2C. This is done by addressing the PCA9558 in a write mode and entering the correct command code. The preset value on the MUX_INx inputs is latched at the command code ACKNOWLEDGE. A REPEATED START is then sent with the R/W bit set to a logic 1, read, and this latched data is read out on the I2C-bus. See Figure 9.
Table 3. Output Port Register (OPR)
Bit Default O7 0 O6 0 O5 0 O4 0 O3 0 O2 0 O1 0 O0 0
This register is an output-only port. It reflects the outgoing logic levels of the GPIO defined as outputs in the IOCR. Bit values in this register have no effect on GPIO defined as inputs. In turn, reads from this register reflect the value stored in the flip-flop controlling the output, not the actual output value.
Table 4. Polarity Inversion Register (PIR)
Bit Default P7 1 P6 1 P5 1 P4 1 P3 0 P2 0 P1 0 P0 0
This register enables polarity inversion of GPIO defined as inputs by the IOCR. If a bit in this register is set to a logic 1, the corresponding GPIO input port is inverted. If a bit in this register is set to a logic 0, the corresponding GPIO input port is not inverted.
2002 May 24
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
S
1
0
0
1
1
1 A0 0
A
0
0
0
0
x
x
x
x
A d7 d6 d5 d4 d3 d2 d1 d0 A
P
SLAVE ADDRESS R/W See Figure 2 for the proper Command Byte
COMMAND BYTE
DATA BYTE
SW00637
Figure 7. I2C write for GPIO registers
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
NO ACKNOWLEDGE FROM MASTER
S
1
0
0
1
1
1 A0 0
A
0
0
0
0
x
x
x
x
A
S
1
0
0
1
1
1 A0 1
A d7 d6 d5 d4 d3 d2 d1 d0 NA P
SLAVE ADDRESS R/W
COMMAND BYTE
SLAVE ADDRESS R/W
DATA FROM SLAVE
SW00638
Figure 8.
I 2C
read for GPIO registers
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
NO ACKNOWLEDGE FROM MASTER
S
1
0
0
1
1
1 A0 0
A
0
0
0
0
1
1
0
0
A
S
1
0
0
1
1
1 A0 1
A
0
0
0 d4 d3 d2 d1 d0 NA P
SLAVE ADDRESS R/W
COMMAND BYTE
SLAVE ADDRESS R/W
DATA FROM SLAVE
SW00639
Figure 9. I2C read of MUX_INx inputs
2002 May 24
8
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
EEPROM write operation
6-bit write operation A write operation to the 6-bit EEPROM requires that an address byte be written after the command byte. This address points to the 6-bit address space in the EEPROM array. Upon receipt of this address, the PCA9558 waits for the next byte that will be written to the EEPROM. The master then ends the transaction with a STOP condition on the I2C. See Figure 10. After the STOP condition, the E/W cycle starts, and the parts will not respond to any request to access the EEPROM array until the cycle finishes, approximately 4 ms. 6-bit read operation A read operation is initiated in the same manner as a write operation, with the exception that after the word address has been written a REPEATED START condition is placed on the I2C-bus and the direction of communication is reversed (see Figure 11). 256 byte write operation (I2C) A write operation to the 256 byte EEPROM requires that an address byte be written after the command byte. This address points to the starting address in the EEPROM array. The four LSBs of this address select a position on a 16 byte page register, the 4 MSBs select which page register. The four LSBs will be auto-incremented after receipt of each byte of data; in this manner, the entire page register can be written starting at any point. Up to 16 bytes of data may be sent to the PCA9558, followed by a STOP condition on the I2C-bus. If the master sends more than 16 bytes of data prior to generating a STOP condition, data within the address page will be overwritten and unpredictable results may occur. See Figure 12. After the STOP condition, the E/W cycle starts, and the parts will not respond to any request to access the EEPROM array until the cycle finishes, approximately 4 ms.
ACKNOWLEDGE FROM SLAVE
256 byte read operation (I2C) A read operation is initiated in the same manner as a write operation, with the exception that after the word address has been written, a REPEATED START condition is placed on the I2C-bus, and the direction of communication is reversed. For a read operation, the entire address is incremented after the transmission of each byte, meaning that the entire 256 byte EEPROM array can be read at one time. See Figure 13. 256 byte EEPROM write to GPIO A mode is available whereby a byte of data in the 256 byte EEPROM array can be written to the GPIO (OPR). This is initiated by the I2C-bus. In this mode, a control word indicating a read from the 256 byte EEPROM and write to the GPIO is sent, followed by the word address of the data within the EEPROM array. Upon ACKNOWLEDGE from the slave, the data is sent to the GPIO. See Figure 14. 256 byte EEPROM write from GPIO A mode is available whereby data in the GPIO (IPR) can be written to the 256 byte EEPROM. This is initiated by the I2C-bus. In this mode, a control word indicating a read from the GPIO and write to the 256 byte EEPROM is sent, followed by the word address for the data to be written. Once the slave sent an ACKNOWLEDGE, the master must send a STOP condition. See Figure 15. After the STOP condition, the E/W cycle starts, and the parts will not respond to any request to access the EEPROM array until the cycle finishes, approximately 4 ms. When the Write Protect (WP) input is a logic 0 it allows writes to both EEPROM arrays. When a logic 1, it prevents any writes to the EEPROM arrays.
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
S
1
0
0
1
1
1 A0 0
A
0
0
0
0
0
1
0
0
A
1
1
1
1
1
1
1
1A
X
X
d5 d4 d3 d2 d1 d0 A
P
SLAVE ADDRESS R/W
COMMAND BYTE
EEPROM ADDRESS
DATA FOR 6bitEEPROM PROGRAMMING BEGINS AFTER STOP
SW00640
Figure 10.
I 2C
write of 6-bit EEPROM
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
NO ACKNOWLEDGE FROM MASTER
S
1
0
0
1
1
1 A0 0
A
0
0
0
0
0
1
1
0
A
1
1
1
1
1
1
1
1A
S
1
0
0
1
1
1 A0 1
A
0
0 d5 d4 d3 d2 d1 d0 NA P
SLAVE ADDRESS R/W
COMMAND BYTE
EEPROM ADDRESS
SLAVE ADDRESS R/W
DATA FROM 6bitEEPROM
SW00641
Figure 11.
I 2C
read of 6-bit EEPROM
2002 May 24
9
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
S
1
0
0
1
1
1 A0 0
A
0
0
0
0
0
0
0
1
A
EEPROM ADDRESS
A
DATA N
A
SLAVE ADDRESS
R/W
COMMAND CODE
AUTO-INCREMENT WORD ADDRESS
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
DATA N+1
A
DATA N+M
A
P
AUTO-INCREMENT WORD ADDRESS
AUTO-INCREMENT WORD ADDRESS
SW00642
Figure 12. I2C page write operation to 256 byte EEPROM; M bytes where M 15
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
S
1
0
0
1
1
1 A0 0
A
0
0
0
0
0
0
1
1
A
EEPROM ADDRESS
A
S
1
0
0
1
1
1 A0 1
A
SLAVE ADDRESS
R/W
COMMAND CODE
SLAVE ADDRESS
R/W
ACKNOWLEDGE FROM MASTER
NO ACKNOWLEDGE FROM MASTER
DATA N
A
DATA N+M
NA P
AUTO-INCREMENT WORD ADDRESS
AUTO-INCREMENT WORD ADDRESS
SW00643
Figure 13.
I 2C
read operation from 256 byte EEPROM; M bytes where M 1
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
NO ACKNOWLEDGE FROM MASTER
S
1
0
0
1
1
1 A0 0
A
0
0
0
x
x
x
x
x
A a7 a6 a5 a4 a3 a2 a1 a0 A
S
1
0
0
1
1
1 A0 1
A d7 d6 d5 d4 d3 d2 d1 d0 NA P
SLAVE ADDRESS R/W
COMMAND BYTE
EEPROM ADDRESS
SLAVE ADDRESS R/W
DATA FROM 256EEPROM DATA LATCHED INTO GPIO REGISTER
SEE FIGURE 2 FOR THE NEEDED COMMAND CODE.
SW00644
Figure 14. Read from 256 byte EEPROM and write to GPIO registers
2002 May 24
10
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
S
1
0
0
1
1
1 A0 0
A
0
0
0
1
0
0
1
0
A a7 a6 a5 a4 a3 a2 a1 a0 A
x
x
x
x
x
x
x
x
A
P
SLAVE ADDRESS R/W SEE FIGURE 2 FOR THE NEEDED COMMAND CODE.
COMMAND BYTE
EEPROM ADDRESS
DUMMY BYTE
GPIO INPUT PORT DATA LATCHED PROGRAMMING BEGINS AFTER STOP
SW00645
Figure 15. Read from GPIO Input Port Register and write to 256 byte EEPROM
RESET Power-on Reset
When power is applied to VDD, an internal power-on reset holds the PCA9558 in a reset state until VDD has reached VPOR. At that point, the reset condition is released and the PCA9558 registers and SMBus state machine will initialize to their default states.
USING THE PCA9558 ON THE SMBus
It is possible to use Intel(R) chipsets to communicate with the PCA9558. There are no limitations when the SMBus Controller is communicating with the Mux or the GPIO; however, there are limitations with the 2K serial EEPROM. Because of being able to address any location in the EEPROM block using the 2nd command byte, the designer using the PCA9558 on the SMBus will have to program around it, an easy thing to do. The device designers had to deal with the specifics of addressing the EEPROM and chose the I2C spec and use the 2nd command byte to address any location in the EEPROM block. In order to write to the EEPROM, write the EEPROM address byte in the Data0 byte and the data to be sent should be placed in the Data1 byte. The Intel(R) chipset's Word Data instruction would then send the address, followed by the command register then Data0 (EEPROM address), and then the Data1 (data byte). A read from the EEPROM would be a two step process. The first step would be to do a Write Byte with the EEPROM address in the Data0 register. The second step would be to do a Receive Byte where the data is stored in the command register. Other differences from the SMBus spec: Paragraph 5.5.5 - Read Byte/Word in figure 5-11 - the PCA9558 follows this same command code with one exception, the PCA9558 requires 2 bytes of command before the repeated start. Paragraph 5.5.6 - Process call in figure 5-15 - the PCA9558 read operation is very similar to the SMBus process call. In the PCA9558 read operation you send a start condition - slave address with a write bit - 2 bytes of command code - repeated start - slave address with a read bit - then read data.
External Reset
A reset of the GPIO registers can be accomplished by holding the I/O_OUT_LOW pin low for a minimum of Tw. These GPIO registers return to their default states until the I/O_OUT_LOW input is once again high.
2002 May 24
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
TYPICAL APPLICATION Applications
* Multi-card systems in Telecom, Networking and Base Station
Infrastructure Equipment
* Board version tracking and configuration * Board health monitoring and status reporting
* Field recall and troubleshooting functions for installed boards * General-purpose integrated I/O with DIP switch and memory
PHILIPS I2C 4 CHANNEL MULTIPLEXER
I2C
ASIC
CONFIGURATION SETTINGS DIP SWITCH OR JUMPER REPLACEMENT
CPU OR C
I2C
PCA9544
BACKPLANE
I2C PCA9558
MUXED EEPROM
I2C
I2C
CONTROL GPIO MONITORING AND CONTROL INPUTS ALARM LEDs EEPROM
CARD ID, SUBROUTINES, CONFIGURATION DATA, OR REVISION HISTORY
SW01080
Figure 16. Typical application A central processor/controller typically located on the system main board can use the 400 kHz I2C/SMBus to poll the PCA9558 devices located on the system cards for status or version control type of information. The PCA9558 may be programmed at manufacturing to store information regarding board build, firmware version, manufacturer identification, configuration option data... Alternately, these devices can be used as convenient interface for board configuration, thereby utilizing the I2C/SMBus as an intra-system communication bus.
2002 May 24
12
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL VDD VI VOUT Tstg PARAMETER DC supply voltage DC input voltage DC output voltage Storage temperature range Note 3 Note 3 CONDITIONS RATING 2.5 to 4.6
PCA9558
UNIT V V V C
-0.5 to VCC +0.5 -0.5 to VCC +0.5 -60 to +150
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VDD PARAMETER DC supply voltage VIL SCL, SCL SDA VIH VOL VOL MUX_OUT_LOW, MUX_IN, _ _ , _, MUX_SELECT MUX_OUT, NON MUXED OUT MUX OUT NON_MUXED_OUT dt/dv Tamb VIL VIH IOL IOH Input transition rise or fall time Operating temperature VOL = 0.4 V IOL= 3 mA IOL= 3 mA IOL= 3 mA IOL= 6 mA CONDITIONS LIMITS MIN 3 -0.5 2.7 -- -- -0.5 2.0 -- -- 0 0 MAX 3.6 0.9 4.0 0.4 0.6 0.8 4.0 4 100 10 +70 UNIT V V V V V V V mA A ns/V C
2002 May 24
13
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
DC CHARACTERISTICS
SYMBOL Supply VDD ICCL ICCH VPOR VIL VIH IOL IOL IIH IIL CI IIH IIL CI Mux A E IIH IIL CI A0 Inputs IIH IIL CI MUX_OUTx VOL VOL IOH VOL VOL IOH GPIO VOL VOL IOH Low Level Output Current Low Level Output Current High Level Output Current (IOL = 100 A) (IOL = 4 mA) (VOH = VDD) -- -- -- -- -- -- 0.4 0.7 100 V V A Low Level Output Current Low Level Output Current High Level Output Current Low Level Output Current Low Level Output Current High Level Output Current (IOL = 100 A) (IOL = 4 mA) (VOH = VDD) (IOL = 100 A) (IOL = 4 mA) (VOH = VDD) -- -- -- -- -- -- -- -- -- -- -- -- 0.4 0.7 100 0.4 0.7 100 V V A V V A Leakage Current High Leakage Current Low Input Capacitance VI = VDD VI = GND -- -- -- -- -- -- 1 -100 10 A A pF Leakage Current High Leakage Current Low Input Capacitance VI = VDD VI = GND -- -- -- -- -- -- 1 -100 10 A A pF Supply Voltage Supply Current Supply Current Power-on Reset Voltage Low Level Input Voltage High Level Input Voltage Low Level Output Current Low Level Output Current Leakage Current High Leakage Current Low Input Capacitance Leakage Current High Leakage Current Low Input Capacitance VI = VDD VI = GND VOL = 0.4 VOL = 0.6 VI = VDD VI = GND Operating mode ALL inputs = 0 V Operating mode ALL inputs = VDD no load; VI = VDD or GND 3.0 -- -- -- -0.5 2 3 6 -1 -1 -- -- -- -- -- -- -- 2.3 -- -- -- -- -- -- -- -- -- -- 3.6 10 10 2.6 0.8 VCC + 0.5 -- -- 1 1 10 1 -100 10 V mA mA V V V mA mA A A pF A A pF PARAMETER TEST CONDITION LIMITS MIN. TYP. MAX. UNIT
Input SCL: Input/Output SDA
MUX_OUT_LOW, WP, MUX_SELECT
NON_MUXED OUT
NOTE: 1. VHYS is the hysteresis of Schmitt-Trigger inputs
NON-VOLATILE STORAGE SPECIFICATIONS
PARAMETER Memory cell data retention Number of memory cell write cycles SPECIFICATION 10 years min 3,000 cycles min
2002 May 24
14
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
AC CHARACTERISTICS
SYMBOL MUX_INx MUX_OUTx tPLH tPHL MUX_SELECT MUX_OUTx tPLH tPHL MUX_OUT_LOW NON_MUXED_OUT tPLH tPHL MUX_OUT_LOW MUX_OUTx tPLH tPHL tR tF CL I2C Bus tSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tSP tSU:STO tR tI CL TW SCL clock frequency Bus free time between a STOP and a START condition Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of SCL clock HIGH period of SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Data spike time Set-up time for STOP condition Rise time for both SDA and SCL signals (10 - 400 pF bus) Fall time for both SDA and SCL signals (10 - 400 pF bus) Capacitive load for each bus line Write cycle time1 10 1.3 600 1.3 600 600 0 100 0 600 20 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 400 -- -- -- -12 -32 10 -100 50 10 300 300 400 -- kHz s ns s ns ns ns ns ns ns ns ns pF mS Output rise time Output fall time Test load capacitance on outputs -- -- 1.0 1.0 -- 20 7.0 -- -- -- 28 15 10 5 -- ns ns ns/V ns/V pF -- -- 20 8 26 15 ns ns -- -- 20 8 28 12 ns ns -- -- 21 7 28 10 ns ns PARAMETER LIMITS MIN. TYP. MAX. UNIT
NOTE: 1. WRITE CYCLE time can only be measured indirectly during the write cycle. During this time, the device will not acknowledge its I2C Address.
2002 May 24
15
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
SDA
tBUF
tLOW
tR
tF
tHD;STA
tSP
SCL
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
SU00645
Figure 17.
MUX INPUT VM VM VIN tPHL tPLZ VCC PULSE GENERATOR RT VOL + 0.3V VOL
VCC
VCC
VOUT D.U.T.
RL
MUX OUTPUT
VM
CL
SW00766
Test Circuit for Open Drain Outputs
Figure 18. Open drain output enable and disable times
DEFINITIONS
RL = Load resistor; 1 k CL = Load capacitance includes jig and probe capacitance; 10 pF RT = Termination resistance should be equal to ZOUT of pulse generators.
SW00767
Figure 19. Test circuit
2002 May 24
16
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm
SOT361-1
2002 May 24
17
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM
PCA9558
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 05-02
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 09889
Philips Semiconductors
2002 May 24 18

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